As transistors have been continuously miniaturized, there have been problems of reduction in drive current (Ion) due to depletion of a polysilicon electrode and increase in gate leakage current due to reduction in thickness of a gate insulating film. To address such problems, there has been a proposal of a MOS transistor that prevents depletion of the gate electrode by using a metal gate electrode made of a metal or other materials and that uses high-dielectric insulating film as a gate insulator to increase its physical thickness and reduce the gate leakage current.
FIG. 1 shows such a semiconductor device. The semiconductor device shown in FIG. 1 includes planar nMOS transistor 21 and pMOS transistor 22. In the semiconductor device, p-type region 23 and n-type region 24 are present in silicon substrate 1.
N-type source/drain region 5 is present in p-type region 23, and silicide layer 6 is provided on source/drain region 5. Gate electrode 8 is provided above part of p-type region 23 with a gate insulating film therebetween. The gate insulating film is comprised of two layers: SiO2 layer 47a on the p-type region 23 side and high-dielectric insulating film 47b on the gate electrode side. Further, gate sidewall 7 is provided on the side of gate electrode 8. P-type region 23, source/drain region 5, gate insulating films 47a, 47b, and gate electrode 8 form nMOS transistor 21.
Similarly, p-type source/drain region 5 is provided in n-type region 24. Gate insulating films 47a, 47b and gate electrode 9 are provided on part of n-type region 24, and gate sidewall 7 is provided on the side of gate electrode 9. N-type region 24, source/drain region 5, gate insulating films 47a, 47b, and gate electrode 9 form pMOS transistor 22.
In the semiconductor device including the planar MOS transistors shown in FIG. 1, it is a conventional practice to change the composition of gate electrodes 8 and 9 so as to control Vth values of the MOS transistors. Use of a high-dielectric insulating film as the gate insulating film and metal silicide as the gate electrode allows Si atoms present in the gate electrode in the vicinity of the gate insulating film to interact with the gate insulating film (Fermi level pinning). As a result, the work function of the material that forms each of the gate electrodes changes, and Vth changes accordingly.
It is therefore a conventional practice to control Vth by changing the composition (Si content) of the metal silicide that forms the gate electrode of each of the MOS transistors to change the degree of the Fermi level pinning.
International Publication No. 2006/001271 and International Electron Device Meeting, Technical Digest, 2004, pp. 91-94 disclose a semiconductor device including pMOS and nMOS transistors that are formed by using a bulk substrate and include high-dielectric gate insulating films. In the semiconductor device, the gate electrode of the pMOS transistor is made of metal silicide having a high metal concentration and the gate electrode of the nMOS transistor is made of metal silicide having a high silicon concentration. The disclosed semiconductor device has a specific configuration in which the gate electrode of the nMOS transistor is made of NiSi or NiSi2 and the gate electrode of the pMOS transistor is made of Ni3Si.
Symposium on VLSI Technology, Technical Digest, 2005, pp. 86-87 discloses a semiconductor device using a bulk substrate. The semiconductor device is characterized by an HfSiON as high-dielectric gate insulating film, an Ni3Si gate electrode of a pMOS transistor, and an NiSi gate electrode of an nMOS transistor.
FIG. 2 shows another example of a semiconductor device of related art. FIG. 2(a) is a top view of the semiconductor device. FIG. 2(b) is a cross-sectional view of the semiconductor device in FIG. 2(a) taken along direction A-A. FIG. 2(c) is a cross-sectional view of the semiconductor device in FIG. 2(a) taken along direction B-B.
The semiconductor device shown in FIG. 2 includes fin-type MOS transistors including protruding semiconductor regions 23 and 24 protruding upward from embedded insulating film 11, and channel regions are formed in semiconductor regions 23 and 24. The semiconductor device is comprised of nMOS transistor 21 and pMOS transistor 22. In the semiconductor device, two protruding p-type region 23 and n-type region 24 are provided on embedded insulating film 11. Gate electrodes 8 and 9 are provided on both sides of p-type region 23 and n-type region 24, respectively.
N-type source/drain region 30a is provided in the both portions in protruding p-type region 23 sandwiching gate electrode 8, and p-type source/drain region 30b is provided in the both portions in protruding n-type region 24 sandwiching gate electrode 9. High-dielectric gate insulating films 47b are provided between p-type region 23 and gate electrode 8 and between n-type region 24 and gate electrode 9.
P-type region 23, source/drain region 30a, gate insulating film 47b, and gate electrode 8 form nMOS transistor 21. Similarly, n-type region 24, source/drain region 30b, gate insulating layer 47b, and gate electrode 9 form pMOS transistor 22.
When MOS transistors 21 and 22 shown in FIG. 2 are in operation, channel regions are formed on the sides of p-type region 23 and n-type region 24.
In the semiconductor device including fin-type MOS transistors shown in FIG. 2 as well, it is a conventional practice to control Vth values of the MOS transistors by changing the composition (Si content) of gate electrodes 8 and 9 so as to change the degree of Fermi level pinning between gate electrodes 8, 9 and gate insulating films 47b. 
In the planar MOS transistor and the fin-type MOS transistor described above, the semiconductor region in which a channel region is to be formed is thick (the length in the direction indicated by reference numeral 25 in FIG. 1 and the length in the direction indicated by reference numeral 26 in FIG. 2). Each of the MOS transistors described above, when operated, therefore functions as a partially depleted MOS transistor (PD-MOSFET) in which the body region is partially depleted.
On the other hand, in recent years, as mobile phone terminals or other apparatus have been equipped with increasingly advanced functions and used in increasingly various applications, there has been a demand for a low-power, high-speed device.
As a low-power, high-speed semiconductor device, a semiconductor device including a fully depleted MOS transistor (FD-MOSFET) in which the body region is fully depleted during operation has received attention.
A semiconductor device including such a MOS transistor can (1) operate at a lower power level due to improvement in S (sub-threshold swing) value, and (2) consume less power due to reduction in substrate leakage current. The semiconductor device can also (3) be faster due to reduction in substrate parasitic capacitance, and (4) operate at a higher speed due to reduction in channel dose (impurity concentration of 1×1014 to 1×1017 cm−3) (improvement in mobility in a working voltage area). The device characteristics can therefore be greatly improved. Among the above device characteristics, the advantageous effect described in (4) allows the short channel effect in a low-channel-dose area to be suppressed, which is a significant advantage obtained by using a fully depleted MOS transistor.